In modern DRAM devices, small dimensions and high capacitance value per unit area of the capacitor are desirable characteristics for achieving a high charge storage capacity. A typical DRAM device includes a field effect transistor and a storage capacitor. When DRAM devices were first developed, planar type storage capacitors which occupy large wafer real estate were used. In modem memory devices where the dimensions of the devices are continuously being reduced, various techniques for reducing the chip real estate usage for a capacitor becomes more critical. One of such methods involves the stacking of a capacitor over the bit line on the surface of a silicon substrate so that the specific capacitance of a storage capacitor can be increased. The stacked capacitor is normally formed by a layer of a dielectric material such as silicon dioxide or oxide-nitride-oxide sandwiched between two layers of a conducting material such as polysilicon. The effective capacitance of the stacked capacitor is increased over that of a conventional planar capacitor based on its increased surface area. Other methods have also been proposed for achieving higher capacitance on limited chip real estate. For instance, one of such methods stores charges vertically in a deep trench. The method therefore requires the formation of a deep trench and as a result, frequently incur significant processing difficulties. Comparatively, the stacked capacitor approach is more superior in achieving higher specific capacitance in a DRAM storage capacitor.
One of the more common configurations of a stacked capacitor is a fin-type stacked capacitor. The fin-type capacitor has a larger surface area and thus a larger charge storage capacity. A typical method for forming such a stacked capacitor can be started by first providing a semiconductor substrate that is of a silicon nature and forming a field oxide region to isolate field effect transistors built on top of the substrate. The field oxide layer is typically formed by a LOCOS method during which silicon is thermally oxidized to form and to expand vertically into a silicon oxide region. The field effect transistors are normally formed by first growing a thin oxide layer on the silicon substrate surface as a gate oxide, and then forming a polysilicon gate electrode on top of the gate oxide layer. The polysilicon layer which forms the gate electrode is also used to form word lines over the field oxide layer for providing interconnections between the transistors and the peripheral circuits on the chip. After lightly doped drain areas are formed in the substrate by an ion implantation method and sidewall spacers are formed on the gate electrode, the transistor formation is completed by forming source/drain contact areas in the substrate adjacent to the gate electrode. A thick insulating layer can be deposited over the gate electrode and the word line for insulation purpose. A silicon nitride etch stop layer can then be deposited over a planarized top surface of the insulating layer. The planarization process for the insulating layer is normally conducted by a chemical mechanical polishing method.
In the conventional fin-type stacked capacitor, the dielectric layers and the conducting layers are deposited by a chemical vapor deposition technique on top of a silicon nitride etch-stop layer. The number of polysilicon layers deposited is dependent upon the number of fins on the stacked capacitor desired. On top of the final dielectric layer, a photoresist layer is deposited and patterned by conventional photolithographic techniques for etching by a plasma dry etch method to form a capacitor cell opening.
The conventional fin-type stacked capacitor fabrication process is complicated and requires multiple deposition steps for forming the multiple layers of oxide and polysilicon on top of an active device. The multiple deposition steps must be conducted in a multiple number of processing chambers and therefore are time consuming and high cost.
It is therefore an object of the present invention to provide a method for forming a DRAM capacitor that has improved charge storage capacity without the drawbacks and shortcomings of the conventional DRAM capacitor fabrication methods.
It is another object of the present invention to provide a method for forming a DRAM capacitor that has improved charge storage capacity by depositing alternating layers of doped and undoped dielectric materials for forming the capacitor cell.
It is a further object of the present invention to provide a method for forming a DRAM capacitor that has improved charge storage capacity by depositing alternating layers of doped and undoped dielectric materials and a photoresist layer capable of generating an acidic reaction product when exposed to UV radiation.
It is another further object of the present invention to provide a method for forming a DRAM capacitor that has improved charge storage capacity by etching different layers of doped and undoped dielectric materials with an acidic compound such that a zig-zagged sidewall in the capacitor cell opening is formed.
It is still another object of the present invention to provide a method for forming a DRAM capacitor that has improved charge storage capacity by etching a cell opening through doped and undoped dielectric layers in an etch chamber that generates UV emission such that an acidic product from a photoresist layer selectively etches the doped dielectric layer more severely than the undoped dielectric layer and thus forming a stepped configuration in the sidewall of the cell opening.
It is yet another object of the present invention to provide a method for forming a DRAM capacitor that has improved charge storage capacity by utilizing a photoresist layer that is capable of generating an acidic reaction product and an etch chamber that generates UV emission during an etching process such that uneven etching on doped and undoped dielectric layers can be achieved.
It is still another further object of the present invention to provide a method for forming a multi-anchor capacitor by depositing alternating layers of doped and undoped oxide materials and a photoresist material capable of generating an acidic reaction product when exposed to UV radiation such that an uneven sidewall in a cell opening can be formed for the multi-anchor capacitor.
It is yet another further object of the present invention to provide a method for forming a multi-anchor capacitor electrode by depositing alternating layers of doped and undoped oxide material and a photoresist material that is capable of generating acidic reaction product when exposed to UV emission in an etch chamber such that a stepped sidewall in a cell opening can be formed for the formation of the multi-anchor capacitor electrode.